1. Field of the Invention
The present invention generally relates to the art of semiconductor fabrication, and more specifically to a novel and useful method for reversing the tone or polarity of a pattern on a semiconductor substrate which has been entitled "REVERSE CASTING BY PLANARIZATION" (RECAP).
2. Description of the Related Art
It is often desirable in the art of semiconductor fabrication to reverse the tone or polarity of a pattern on a substrate or other device layer for purposes including modification of the layer underlying the pattern. Such a technique is especially valuable in the production of self-aligned channel-stop and well implants in 0.5 micrometer bulk CMOS circuits. The Hughes Aircraft Company discloses a "quadruple-well" CMOS process in U.S. Pat. No. 4,633,289 which enables the design of high packing density and superior device performance, to which the application of the present invention provides an immediate and substantial advantage.
The level of integration attainable in integrated circuit fabrication is directly limited by the density to which individual devices (transistors, resistors, capacitors, etc.) may be packed on a chip. The packing density in turn is directly limited by a number of factors, two of which are relevant to the present invention: device isolation and pattern alignment.
In order to prevent short circuiting of adjacent device elements, it is necessary that the devices be electrically isolated from each other. Device isolation has been one of the most important problems associated with the fabrication of integrated circuits. With increasing packing density for very large scale integration (VLSI) applications, the problem of device isolation can fundamentally limit circuit design.
A variety of different methods have been employed in the development of the technology for device isolation. The local oxidation of silicon (LOCOS) process has been commonly used for the isolation of active devices in silicon metal oxide-semiconductor (MOS) integrated circuit. The process is described in the paper by E. Kooi, J. G. Van Lerop, and J. A. Appels, entitled "Formation of silicon nitride at a Si--SiO.sub.2 interface during local oxidation of silicon and during heat treatment of oxidized silicon in NH.sub.3 gas, " in J. Electochem. Soc. Vol. 123. pp. 1117-1120, 1976. However, applying the LOCOS process to VLSI circuits is severely limited by field oxide encroachment (the bird's beak phenomenon) and by lateral diffusion of channel stop dopants into the active device areas. Both effects overtake the active area near the channel edges; hence, the physical channel width becomes less than the desired channel width. The difference between physical and designed channel widths becomes significant when devices are scaled down for VLSI applications. This channel-narrowing effect increases the FET threshold voltage and reduces its current driving capability. In order to achieve the desired channel width, the corresponding mask dimension must be drawn oversized, which results in wasted layout area.
Various improved techniques have been proposed to reduce the bird's beak and lateral diffusion phenomenon, but generally achieve the desired device structures at the expense of added process complexity. Lift-off techniques, which are the reverse of photolithography with etching, have also been used for device isolation. The goal of using lift-off techniques is to achieve self alignment for higher packing density. "Self alignment" refers to the non-overlap of the channel and channel stop implants and/or other laterally adjacent pattern areas. It results in a sharp boundary between the two because there is only a single patterning exposure during the lift-off process. Lift-off isolation techniques provide greatly improved field isolation for MOSFETs (metal oxide-semiconductor field effect transistors).
A conventional thick-metal lift-off process, in which a metal film is evaporated onto a patterned resist layer and the resist layer subsequently dissolved to "lift-off" the metal film over the resist layer, thereby exposing the underlying substrate and forming a reverse image constituted by the remaining metal, depends on specially prepared materials, and there is also a concern about the reliability of the process as applied to VLSI fabrication. The resist tends to harden under reactive ion etching, making it more difficult to dissolve. Also, the naturally resulting geometry of the resist and overlying thick metal layer at the boundaries between the active areas and channel stops can impede a solvent from getting to the resist. For these reasons, lift-off of thick metal is often difficult to reproduce reliably. For reference purposes, a lift-off process for NMOS circuits using relatively thick (700 nm) aluminum has been reported by J. Y. Chen, R. C. Henderson, and D. E. Snyder in the paper "A novel self-alignment isolation process for VLSI" in IEEE Trans. Electron Devices, ED-30, No. 11, pp. 1521-1527, 1983.
As illustrated in FIG. 1a of the accompanying drawing, the generic prior art thick metal lift-off process utilizes a semiconductive wafer substrate 10 formed of silicon or other appropriate material. A sacrificial patterned layer 12 is applied to the substrate 10, the pattern corresponding to devices such as transistors, resistors, etc. to be integrated into the circuit. The patterned layer 12 typically comprises a known photoresist material such as AZ1350J, manufactured by the Hoechst Celanese Company of Somerville, N.J., and is patterned by photolithography.
The next step of the process is illustrated in FIG. 1b in which a relatively thick metal film 14 comprising, for example, 700 nm of aluminum or 400 nm of gold, is evaporated onto the surfaces of the substrate 10 and patterned layer 12. The final step of the process is illustrated in FIG. 1c in which the patterned layer 12 is dissolved away using a solvent such as acetone. Dissolution of the patterned layer 12 releases the metal film 14 which is formed thereon, causing the metal film 14 to be "lifted-off" the substrate 10. The resulting structure consists of the substrate 10 and metal film 14 on areas of the substrate 10 which were exposed directly to the metal film evaporation (not masked by the photoresist patterned layer 12).
Although the metal film lift-off method is inherently self-aligning, the resist pattern must be formed with extremely precise vertical or undercut wall profiles to be applicable to VLSI fabrication. The metal evaporation must be well collimated and normal to the wafer surface to prevent deposition on the resist sidewalls. The lift-off process is also prone to particulate contamination and formation of gaps between the resist and metal as discussed hereinabove.
The reverse-tone image is constituted by the areas of the metal film 14 which remain after performing the dissolution step illustrated in FIG. 1c. The reversal process enables implantation or other desired operation to be performed on the exposed (reversed) areas of the substrate 10.
An improvement to the thick metal lift-off process is disclosed in U.S. patent application Ser. No. 66,800, filed June 25, 1987 abandoned. The process is entitled "SELF-ALIGNED ISOLATION" (SAIL), and utilizes thin metal lift-off. In the process, a field oxide is grown first, followed by a channel stop implant that is self-aligned to the active area by means of a lift-off process that utilizes only thin metal. The self-alignment of channel stop implant to active area is shown to improve the breakdown voltage of MOSFET devices. Direct window isolation is used to reduce oxide encroachment and reduce out-diffusion of boron channel stop implant into the active area. As a result, the narrow width effect is minimal. Since thin metal liftoff can be performed reproducibly, the SAIL process is described as a high-yield process for VLSI fabrication.
Although the SAIL process constitutes a major improvement over conventional thick metal lift-off, good lift-off places stringent requirements on the resist wall profile. Gaps between the resist and metal inevitably occur, thereby limiting the isolation and alignment efficiency as well as the packing density achievable by the fabrication process.